I am reverse engineering ancient Sharp plasma display panel (LJ640U35, with LZ93N34 controller) and spent lots of time tweaking timings of selfmade video controller (Altera MAX3 epm3256aqc CPLD) and discovered bad grounding problems. Pixel clock is about 6MHz, logic master clock is 50MHz, but there is problems with connection between “video controller” and ATMEGA control board.
Post time: Feb-06-2017